Artificial neural networks have long been used in the field of artificial intelligence as models of biological neural processing. In the past, neural networks have been implemented in software coupled with traditional Von Neumann architecture computing hardware, such as central processing units (CPUs) or graphic processing units (GPUs). Such implementations may require vast amounts of storage space and power.
Accordingly, there has been pressure over the years to move toward using more efficient, specialized hardware technologies. More recently, hybrid complementary metal-oxide semiconductor (CMOS) circuits with integrated memristive devices, also referred to as “memristors”, have emerged as one alternative [1]. Memristive devices are well-suited for implementing synaptic weights in neural networks due to their resistive switching characteristics being able to model the synaptic weights in analog form. However, neural networks with integrated memristive devices introduce new challenges in training the neural networks in view of non-linear kinetics present in typical memristive devices [2].
One approach has been to implement ex-situ training where a simulated neural network is trained in software, and the weights are then imported into the CMOS-memristive hardware [3]. However, there is a concern this approach may not adequately account for hardware variability since online training is not performed. As a result, there is a concern that the hardware neural network may underperform with respect to the software simulation.
Conversely, one approach for implementing in-situ training of CMOS-memristive hardware includes performing closed-loop, tuning controls to account for the non-linear kinetics of memristive devices [3, 4]. In this case, there is a concern that this in-situ training approach may not be viable for more complex many-layer neural networks or complex training algorithms (e.g., backpropagation [5]). This is because closed-loop, tuning control processes may be time-consuming and the feedback circuitry is complex. As a result, there is a concern that this approach may not scale at a practical rate.
For the above reasons, recent in-situ training of CMOS-memristive hardware focuses mainly on spike-timing-dependent plasticity (STDP) or delta-rule [3] for learning. However, these training rules may not provide a robust solution for more demanding applications (e.g., automotive or aerospace), since backpropagation is widely regarded as the fundamental training algorithm for many-layer neural networks [5].